1. Field of the Invention
The present invention relates to a frequency multiplier, and in particular, to a frequency multiplier for generating a high frequency signal such as a clock signal.
2. Background of the Related Art
In general, higher frequency circuits are being increasingly used. Therefore, a high frequency clock signal is needed for such high frequency circuits. However, when generating a high frequency signal using a crystal oscillation method, jitter is increasingly generated. To avoid the jitter problem, one related art method multiplies an intermediate frequency after changing a frequency to the common intermediate frequency.
The frequency multiplier is a circuit for generating a high frequency clock signal. The frequency multiplier circuit can be used in a memory, a microprocessor, a video appliance, an audio appliance, etc. During use, the frequency multiplier is connected in a chip of a clock recovery circuit. Therefore, the frequency multiplier is an element effecting the complexity of the construction and the operational stability of the circuit.
Related art frequency multipliers may be classified into frequency multipliers that use a Phase Locked Loop (PLL) and frequency multipliers that use a Delay Locked Loop DLL).
The related art frequency multiplier using a PLL, as shown in FIG. 1, includes a phase frequency detector (PFD) 10 for detecting a phase/frequency difference between an input signal f1 and a feed-back signal. A loop filter (LF) 11 outputs a control signal in accordance with the difference detected by the phase frequency detector 10. A voltage-controlled oscillator (VCO) 12 is oscillated by the control signal from the loop filter 11 to output a frequency signal. A divider 13 divides the frequency of the signal from the voltage-controlled oscillator 12 and feeds-back the frequency-divided signal as the feed-back signal to the phase frequency detector 10.
The phase frequency detector 10 is implemented by an exclusive OR-gate XOR. The exclusive OR-gate XOR detects a phase difference during the pulse duration of the input signals when the frequency of the signals are close to each other. However, since most commonly used input signals do not have a 50% duty cycle during the pulse duration, the output from the exclusive OR-gate XOR does not have a uniform duty cycle.
When the common pulse durations are identified with each other, the pulse durations between the rising edge and the falling edge are identical. Thus, when the common pulse durations are identical, an edge-triggered phase detector is generally used. Among the edge-triggered phase detectors, a phase frequency detector 10 is generally used.
In addition, the divider 13 includes a T-flip-flop, and the loop filter 11 includes a capacitor formed of an MOS FET gate and a large size capacitor having an n-well to overcome the jitter problem.
The operation of the related art frequency multiplier using the PLL will now be described. First, when a signal having a frequency f1 is inputted, the phase frequency detector 10 detects the difference between the frequency f1 of the input signal and the feed-back signal. Then, the loop filter 11 outputs a control signal corresponding to the frequency difference detected. The loop filter 11 acts as a low pass filter and stabilizes the circuit.
The voltage-controlled oscillator 12 is oscillated by the control signal from the loop filter 11. Thus, the voltage-controlled oscillator 12 outputs a signal having a frequency determined by the control signal. The divider 13 divides the frequency of the signal from the voltage-controlled oscillator 12 and feeds-back the frequency-divided signal to the phase frequency detector 10. When the input signal and the feed-back signal are accurately phase locked and the divider 13 is a one-half divider, then the signal from the voltage-controlled oscillator 12 is a doubled frequency 2f1 relative to the input signal frequency f1.
However, the related art frequency multiplier using a PLL requires a loop filter for stabilizing the PLL circuit. In addition, a large size capacitor is used in the loop filter LF to secure the desired circuit stability. If the capacitance of the loop filter capacitor is increased to improve stability, the capacitor undesirably occupies a larger area in the circuit. Therefore, it is difficult to effectively design the multiplier.
In addition, the related art PLL frequency multiplier uses a voltage-controlled oscillator 12. The voltage-controlled oscillator 12 may be formed of a current starved ring oscillator, a variable capacitor ring oscillator, a variable resistor ring oscillator, and a current-controlled relaxation oscillator.
Important criteria in a voltage-controlled oscillator include a linear characteristic and noise generation level. The operational range of the current starved ring oscillator is wide, but it requires a boot-up circuit and has a poor linearity. The variable capacitor ring oscillator has a noise eliminating effect, it requires an additional circuit such as a bias mirror circuit, a supply independent circuit or the like.
As the construction of the related art voltage-controlled oscillator becomes complicated, additional circuits are required for stable operation and noise occurs. Further, to secure the operational stability and prevent noise occurrence, a loop filter must be included in the frequency multiplier.
To overcome the structural complexity and noise occurrence problems, a frequency multiplier using the Delay Locked Loop (DLL) can be considered as an effective circuit. FIG. 2 illustrates a related art frequency multiplier using a DLL.
As shown in FIG. 2, the related art DLL frequency multiplier using includes a phase detector (PD) 20 for detecting a phase difference between an input signal and a feed-back signal. A loop filter 21 outputs a control signal in accordance with the phase difference detected by the phase frequency detector 20, and a voltage-controlled delay (VCD) line 22 varies the delay ratio of the input signal in accordance with the control signal from the loop filter 21 and feeds-back the delayed signal to the phase detector 20. The voltage-controlled delay line 22 includes four unit delay cells DC1 through DC4 that act as an inverter. The input signal and the output signal from the first unit delay cell DC1 are applied to the inputs of an exclusive-OR gate 23.
The operation of the related art DLL frequency multiplier will now be described. First, when a signal having a frequency f1 is inputted, the phase detector 20 detects a phase difference between the input signal and the feed-back signal. The loop filter 21 outputs the control signal corresponding to the detected phase difference to the voltage control delay line 22. The four unit delay cells DC1 through DC4 of the voltage-controlled delay line 22 adjust the delay ratio of the input signal to vary the phase in accordance with the control signal from the loop filter 21.
The four unit delay cells DC1 through DC4 output signals that are generated by quarter-dividing the input signal in one period. The input signal and the output from the delay cell DC1, which has a 1/4 period difference, are exclusively ORed by the exclusive-OR gate (XOR) 23 to generate a doubled frequency 2f1.
The input for the exclusive-OR gate XOR 23 is not limited to the input signal and the output signal from the delay cell DC1. The outputs from the unit delay cells DC1 through DC4, which have a 1/4 period difference, can be used as the input to the exclusive-OR gate 23.
The construction of the related art DLL frequency multiplier is simple. However, the related art DLL frequency multiplier has various disadvantages. The multiplier has a duty cycle problem because of the exclusive-OR gate 23. In addition, a jitter problem occurs because of the pulse duty cycle that is a critical problem to the performance of the frequency multiplier. In order to eliminate the jitter problem, additional circuitry is necessary.